A simple and effective scheduling mechanism using minimized cycle round robin

packet and cell switched networks. We demonstrate that MCRR exhibits optimal worst-case latency property in a certain class of weighted round robin (WRR) approaches which are currently used for packet (cell) scheduling in high-speed networks, such as ATM networks. We further present a Hierarchical MCRR (HMCRR) mechanism to maximize the efficacy of MCRR in practice and be scalable to large number of connections. HMCRR can significantly improve router/switch scheduling latency and hence the delay and delay jitter performance, while keeping the simplicity of WRR based scheduling disciplines. I. INTRODUCTION In high-speed broadband networks, the ability to provide with quality of service (QoS) guarantees for diverse applications is crucial and challenging. QoS usually include the parameters such as effective bandwidth, bounds of end-to-end delay, delay jitter, and packet or cell loss rate. The scheduling algorithms adopted in router/switch play an important role for QoS mechanism in packet and cell switched networks, and hence attract a lot of attentions from both research community and telecommunications industries. Basically, two categories of scheduling schemes can be classified: Round Robin (RR) based approaches and Generalized Processor Sharing (GPS) based approaches. RR based approaches include weighted round robin (WRR) [1, 2], deficit round robin (DRR) [3], carry-over round robin (CORR) [4], and hierarchical round robin (HRR) [5]. GPS based approaches include WFQ [6, 7], worst-case fair weighted fair queueing (WF 2 Q) [8], virtual clock (VC) [9], self-clocked fair queueing (SCFQ) [10] and start-time fair queueing [11].